Ever more stringent requirements with regard to the reduction of switching losses are made of power semiconductor components. In the case of MOSFETs, in particular, a significant proportion of the switching losses is caused by parasitic capacitances. In order to reduce the parasitic gate-drain capacitance, therefore, the overlap region between the gate electrode and drain region is kept as small as possible. As an example of this, reference is made to the so-called “dual-poly” concept, wherein a gate electrode and a field electrode are arranged in a trench MOSFET.
In the “dual-poly” concept, however, an additional parasitic capacitance is manifested between the gate electrode and the field electrode and, in the case of a high field electrode resistance, can lead to the gate electrode being coupled to the field electrode. In the case of a so-called “buck converter”, for example, this fosters a situation in which the MOSFET is switched on again at the low-voltage terminal. However, this process of switching on again would lead to additional switching losses. Consequently, there is the requirement for providing a “dual-poly” content having a low gate-field electrode capacitance. This can be achieved, for example, by means of a thick dielectric layer (insulation layer) between the gate electrode and the field electrode. However, the production of such a thick dielectric layer (insulation layer) proves to be difficult on account of the structural boundary conditions in the case of a power semiconductor component.
There is a need to provide a method for producing a thick insulation layer between two electrodes in the trench of a semiconductor body.